1. Field of the Invention
The present invention relates to a method and apparatus for fabricating a metal layer on a substrate, and more particularly, to a method and apparatus for fabricating a metal layer on a substrate using electrochemical deposition (ECD)
2. Description of the Related Art
Conductive interconnections on integrated circuits typically take the form of trenches and vias in the background art. In modern deep submicron integrated circuits, the trenches and vias are typically formed by a damascene or dual damascene process. Copper is currently used in ultra large scale integration (ULSI) metallization as a replacement for aluminum due to its lower resistivity and better electromigration resistance. Electrochemical copper deposition (ECD) has been adopted as the standard damascene or dual damascene process because of larger grain size (good electromigration) and higher deposition rates. More particularly, electroplating is well suited for the formation of small embedded damascene feature metallization due to its ability to readily control growth of the electroplated film for bottom-up filling, and the superior electrical conductivity characteristics of the electroplated film.
FIGS. 1A–1D illustrate a typical metallization technique for forming interconnect features in a multi-layered substrate of the background art. Generally, the method includes physical vapor deposition of a barrier layer over the feature surfaces, physical vapor deposition of a conductive metal seed layer, preferably copper, over the barrier layer, and electroplating of a conductive metal, preferably copper, over the seed layer to fill the interconnect structure/feature. The deposited layers and the dielectric layers are then planarized, such as by chemical mechanical polishing (CMP), to define a conductive interconnect feature.
In FIG. 1A, a semiconductor substrate 10 is provided. A copper metal interconnect 20 is shown patterned within an insulating layer 25, i.e., silicon oxide. In addition, a dielectric layer 30 is deposited and patterned with a via portion 32 and a trench portion 34. The dual damascene structure is thus formed including a via portion 32 and a trench portion 34. Although a dual damascene structure is illustrated in FIGS. 1A–1D, other types of interconnect features are also typically metallized using this technique.
In FIG. 1B, a barrier layer 42, preferably including tantalum (Ta) or tantalum nitride (TaN), is deposited over the surface of the dielectric 30, including the surfaces of the via portion 32 and the trench portion 34. A copper seed layer 44 is deposited over the barrier layer 34 using physical vapor deposition (PVD). The copper seed layer 44 provides good adhesion for a subsequently electroplated copper layer.
In FIG. 1C, a copper layer 50 is electroplated over the copper seed layer 44 to metallize the dual damascene structure. However, the electroplating metallization process presently practiced may yield voids 52 and 54, some of which can even reach the barrier/seed layer, possibly leading to defective or prematurely exhausted devices.
In FIG. 1D, the top portion of the processed substrate, i.e., the exposed electroplated copper layer 50 (shown in FIG. 1C), is then planarized, preferably by chemical mechanical polishing (CMP). During planarization, portions of the copper layer 50, copper seed layer 44, barrier layer 42, and a top surface of the dielectric layer 30 are removed from the top surface of the substrate, leaving a fully planar surface with conductive interconnect features, such as the dual damascene structure.
However, the present inventors have determined that there are problems relating to the quality of the deposited metal film. One challenge facing damascene and dual damascene processing is the formation of defects, such as pits, voids and swirling defects. A number of obstacles impair defect-free electrochemical deposition of copper onto substrates having submicron, high aspect features. Therefore, it is important that the electroplating surface is uniform and reliable to ensure defect-free deposition. As seen in FIG. 2, some processed wafers 10, experience swirling defects D after electrical plating due to surface contamination. Even after preventive maintenance, the defect problem still occurs which can negatively impact yield rate.
U.S. Pat. No. 6,395,642 (Liu et. al.), the entirety of which is hereby incorporated by reference, describes an integrated process of plasma cleaning of the structure prior to the electroplating of copper. NH3 plasma or, H2/N2 thermal reduction can be employed. The integrated process promotes controlled electrochemical deposition (ECD) of copper for solid filling of the trench.
In addition, the electrochemical copper deposition (ECD) process is a wet process. Poor wettability between wafer plating surfaces and the electrolyte causes voids in the trenches and vias, as copper is electroplated and grows from all sides onto the seed layer. Another difficulty inherent in immersion of the wafer in a plating solution is air bubbles occurring on the wafer surface, which may disrupt the flow of electrolytes and electrical current to the wafer plating surface impacting uniformity and function of the deposited layer. A conventional method of reducing air bubble function immerses the wafer vertically into the plating solution. However, mounting the wafer vertically for immersion into the plating solution adds complexity and hinders automation of the electroplating process. Accordingly, it is desirable to have an apparatus for electroplating a wafer that avoids air bubble occurrence.
U.S. Pat. No. 6,582,578 (Dordi et. al.), the entirety of which is hereby incorporated by reference, describes an electrochemical plating (ECP) system that limits the formation of air bubbles between the substrate and/or the substrate holder assembly during immersion of the substrate into the electrolyte solution. A substrate is immersed in the electrochemical plating system tilting the substrate at immersion reducing trapping or formation of air bubbles between the substrate and the substrate holder assembly. However, even using the cited method, it is difficult to eliminate all micro-bubbles. The electrolyte may also evaporate during ECP, and the vapor can easily condense on other unprocessed wafers. These deleterious effects with electrochemical copper deposition usually cause reliability problems, such that it is important to prevent contamination of the electroplating surface from the electrolyte.
Another conventional method to solve on or more of the aforementioned problems is to anneal the copper film under atmospheric pressure or less. U.S. Pat. No. 6,399,486 (Chen et. al.), the entirety of which is hereby incorporated by reference, describes a special annealing process to remedy electrochemical copper deposited (ECD) defects in a dual damascene via and trench structure. The annealing conditions utilize special annealing steps to promote low temperature copper surface diffusion to remedy the voids and other defects within the copper trench and via structure. Annealing takes place at approximately 300 to 500° C., under nitrogen N2, hydrogen H2 gases (reducing atmosphere to remove copper oxide, N2/H2 plasma preferred), approximately 100 MPa to 600 MPa, for approximately 0.5 to 10 minutes. These conditions take advantage of low temperature surface diffusion mechanisms. However, voids are not completely eliminated during these conventional annealing processes.